Conventional non-volatile semiconductor devices include various types of flash memory devices, electrically programmable read only memory (EPROM) devices and electrically erasable programmable read only memory (EEPROM) devices. Such conventional types of semiconductor devices are generally characterized by a floating gate and an electrical connection called a control gate, typically fabricated from polycrystalline silicon doped with an appropriate doping material to render the polycrystalline conductive, e.g., phosphorous. The floating gate is separated from a substrate region by a gate dielectric or tunnel dielectric layer of insulating material while the substrate region includes symmetrical or asymmetrical source/drain regions defining a channel region therebetween. The floating gate and control gate are typically separated by a layer of insulating material.
EEPROMs are typically programmed by applying a voltage to the control gate so that electrons or a charge tunnels through the tunnel oxide layer and is stored on the floating gate in a capacitive manner. Erasing is implemented by grounding the control gate and causing electrons or charge to tunnel through the tunnel dielectric layer to the substrate. Typically, electrons tunnel through the tunnel dielectric layer by a phenomenon called "Fowler-Nordheim" tunneling. A conventional EEPROM is disclosed by Mukherjee et al., U.S. Pat. No. 4,868,619 and comprises an asymmetrical drain-source junction as illustrated in FIG. 4.
Adverting to FIG. 4, shallow drain region 54 is formed in substrate 52 at a shallower depth than source region 56. Channel 58 is defined between source 56 and drain 54. Source 56 is a double diffused region comprising a deep phosphorous region 80 and a shallow arsenic region 78. Gate dielectric 60 is formed over channel 58 and extends between drain 54 overlapping a portion 62 of source 56. The gate dielectric 60 is relatively uniformly thin over its entire cross section. Floating gate 64 is formed over gate dielectric 60, and a second dielectric layer 66 is formed over floating gate 64. Control gate 68 is then formed over dielectric layer 66. In operation, programming of the EEPROM depicted in FIG. 4 is achieved by raising the drain 54 and control gate 68 to predetermined potentials above that of the source 56, so that hot electrons 32 are generated and accelerated across the gate dielectric 60 onto floating gate 64. Erasing is achieved by floating the drain node 54, holding the control gate 68 at ground potential, and applying a pulse of high voltage to the source 56. Dielectric layer 66 typically comprises a material having a high dielectric constant, i.e., greater than about 5, such as tantalum pentoxide or silicon nitride. Gate dielectric 60 typically has a thickness of about 100 .ANG. to about 200 .ANG. and comprises an oxynitride. Overlap region 62 is maintained small, e.g., about 0.3 to about 0.4 micrometers. Fowler-Nordheim tunneling requires a very thin dielectric layer, thereby necessitating a gate dielectric 60 thickness of about 100 .ANG. to about 200 .ANG..
The escalating demands for high densification and performance associated with ultra large scale integration semiconductor devices requires design features of 0.25 microns and under, increased transistor and circuit speeds, sharp junctions, high reliability and increased manufacturing throughput for competitiveness. The reduction of design features to 0.25 microns and under generates numerous problems challenging the limitations of conventional semiconductor technology.
Non-volatile semiconductor devices, such as the EEPROM depicted in FIG. 4, occupy a significant amount of precious real estate on a semiconductor substrate and, hence, pose a serious impediment to miniaturization. Moreover, the protrusion of the gate electrodes above the main surface of a substrate results in the formation of a significant step portion which is difficult to planarize, thereby challenging the depth of focus limitations of conventional photolithographic techniques.
Accordingly, there exists a need for reliable non-volatile semiconductor devices having design features of less than about 0.25 microns. There also exists a need for reliable non-volatile semiconductor devices having substantially uniform topography.